The present invention relates to bit synchronizers and methods of synchronizing and calculating error.
Radio frequency (wireless) communications systems are known in the art. Radio frequency communications systems typically include a transmitter and a receiver. Other communications systems are bidirectional and include a first transponder that can send or receive a radio frequency communication, and a second transponder that can receive the radio frequency communications from the first transponder and transmit signals, via radio frequency, back to the first transponder.
Radio frequency identification devices define another form of bidirectional communications systems. As large numbers of objects are moved in inventory, product manufacturing, and merchandising operations, there is a continuous challenge to accurately monitor the location and flow of objects. Additionally, there is a continuing goal to interrogate the location of objects in an inexpensive and streamlined manner. One way of tracking objects is with an electronic identification system.
One electronic identification system utilizes an RF transponder device affixed to an object to be monitored. An interrogator is provided to transmit an interrogation signal to the device. The device receives the signal, then generates and transmits a responsive signal which may identify the device. The interrogation signal and the responsive signal are typically radio-frequency (RF) signals produced by an RF transmitter circuit. Since RF signals can be transmitted over greater distances than magnetic fields, RF-based transponder devices tend to be more suitable for applications requiring tracking of a tagged device that may not be in close proximity to an interrogator. For example, radio frequency based transponder devices tend to be more suitable for inventory control or tracking.
Synchronization of a particular receiving device (e.g., the interrogator) of a communication system to the data signal being received is necessary to achieve optimal sampling of the received data signal. Optimized sampling of the received data signal minimizes error rates. In prior art analog communication systems, phase lock loops including loop filters and voltage controlled oscillators are typically used to align a clock with phasing of incoming data.
Some wireless communication systems communicate via digital data transmissions. Communicating via a digital format provides numerous advantages including encoding, various modulation techniques, etc. Optimal sampling of the received signal provides reliable reception of the data at the receive side of such digital systems.
Problems often experienced in this art include the monitoring of error such as separation of the sampling signal from the received data signal. Further problems include maintaining proper alignment of the sampling signal with the received data signal during reception of the entire data signal.
Therefore, it is desirable to provide a communication system which achieves the benefits of digital communication while overcoming the problems associated therewith.
A first aspect of the present invention provides a bit synchronizer configured to generate a timing signal for optimizing the sampling of a received data signal. One embodiment of the bit synchronizer comprises an error generator, a bit clock generator and history circuitry. The timing signal preferably has a frequency approximately equal to the bit rate of the data signal. In addition, the bit synchronizer is configured to detect error of the timing signal with respect to the data signal and adjust the timing signal responsive to the detection of error. Further, the history circuitry of the described bit synchronizer accumulates error to define a history. The bit synchronizer utilizes the history to update the timing signal during portions of the data signal having insufficient timing information.
The present invention also provides methods of synchronizing. Some methods of synchronizing include synchronizing a timing signal, such as a bit clock signal, with a received data signal. One method of synchronizing according to the present invention comprises providing a data signal having a first portion and a second portion and generating a timing signal. The method further provides first adjusting the timing signal during the first portion of the data signal and accumulating a history value during the first portion of the data signal. The described method provides second adjusting the timing signal during a second portion of the data signal using the history.
Another method of synchronizing comprises providing a data signal including digital information and deriving timing information during a first portion of the data signal. Further, the method provides generating a timing signal, detecting an absence of timing information during a second portion of the data signal, and adjusting the timing signal during the second portion of the data signal. This described embodiment utilizes a specified digital value to derive timing information. Sufficient timing information is typically absent when the specified digital value is not received.
The invention provides methods of calculating error of a timing signal with respect to a data signal. The described method includes receiving a data signal containing plural digital values and first analyzing the data signal corresponding to a first portion of a selected digital value of the data signal. The method also includes providing a first reference value responsive to the first analyzing. One aspect of the method includes second analyzing the data signal corresponding to a second portion of the selected digital value of the data signal and providing a second reference value responsive to the second analyzing. Following the analyzings, the method includes comparing the first reference value with the second reference value.